Sai Poojitha Palem

Sai Poojitha Palem

No headline available | Bengaluru, Karnataka, India

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Work Experience

Wipro

Senior Design Verification Engineer

Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Wipro

Design Verification Engineer

Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Signoff Semiconductors

Digital Design Engineer

Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Cyient

FPGA Design Intern

Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Maven Silicon

ASIC Design and Verification

Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

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